1. Field of the Invention
The present invention relates to a defect analysis place specifying device, a defect analysis place specifying method, a program for specifying a detect analysis place and a recording medium recorded with a program for specifying a defect analysis place, and particularly to a defect analysis place specifying device, a defect analysis place specifying method, a program for specifying a detect analysis place and a recording medium recorded with a program for specifying a defect analysis place that can specify a high-priority defect analysis place to efficiently improve the quality of products.
2. Description of the Related Art
A defective place specifying method in a surface mounting device has been disclosed in Japanese Patent No. 3,511,632 (paragraph no. 0009, etc. ), Japanese Patent No. 3,514,486 (paragraph no. 0009, etc.), etc. According to the method disclosed in the former Japanese Patent, defective places of printed wiring boards are individually analyzed every defective place and every printed wiring board to calculate the degree of incidence of the final defect by each step, and a cause for the defect is automatically predicted. According to the method disclosed in the latter Japanese Patent, when defective places are analyzed, the efficiency is enhanced by actively utilizing a condition reflecting a previous analysis result, thereby shortening the defect factor specifying time and enhancing the working efficiency.
The defective place specifying method of an electronic part mounting device has been hither carried out as described above. In order to reduce the defective fraction in the electronic part mounting device with the minimum time and effort, it is required to specify a defective place having a high defective fraction at an early stage and take a countermeasure to the defective place concerned.
However, in the former Japanese Patent, the defective places of each printed wiring board are individually analyzed one by one to estimate the causes of the defects (hereinafter referred to as “defect factor”), and thus it takes much time to perform the estimation of the defect factors, and also when countermeasures to the defect factors thus estimated are successively taken in turn, it takes more time to cover a desired defective fraction. Furthermore, in the latter Japanese Patent, the processing is efficiently executed, however, this method pays no attention to efficient enhancement of the quality of products with respect to the electronic part mounting device.
Furthermore, in order to efficiently enhance the quality of products, it is required to specify a set of defective places which can be estimated to be caused by a common defect factor and determine an analysis target from the defective places thus estimated. However, this method is very difficult for persons other than skilled persons.